![]() ![]() In remote loopback, data input by RTIP and RRING is transmitted back to TTIP and TRING through the jitter attenuator. When the RLB bit of the control register is set to high, the remote loopback is enabled. When the RLB bit of the control register is set to low, then remote loopback is disabled. From the far end equipment, the signal loops through the LIU and the jitter attenuator. This loopback allows the user to test the far end of the equipment link. There are six types of loopback supported by Maxim T1/E1/J1 transceivers. The signals from both ends can be compared and any discrepancy helps to trace the fault. In loopback mode, the device loops the signal from one end of the device to the other end of the sending device, after it has passed through a network or across a particular link. Loopback modes are useful for diagnostic testing of the device or equipment. T1 and E1 are terms used to refer to the transmission of 1.544Mbps and 2.048Mbps over any media. This application note contains an overview of the loopback functions for Maxim T1/E1/J1 transceivers. The discrepancy between the two helps to trace the fault. ![]() The signals from both ends can be compared. In loopback mode, the device loops the signal from one end of the device to the other end of the sending device after it has passed through a network or across a particular link. I also meet this problem using Braswell Platform, We will be reporting the problem to Intel. The problem seems more frequent when the host controller is under high load. There is also some evidence that the problem might also be linked to load. It wouldn't be too surprising if the problem also effected other devices but we haven't done extensive testing on 3rd party devices. ![]() In summary there seems to be a compatibility bug between some Intel system on a chip (SoC) USB3 host controllers and at least the Cypress FX3 device chip. This unexpected behaviour confuses the USB devices, it could be argued that that our plug should eventually recover from this bad behaviour, but the problem is really in the underlying silicon chip (a Cypress FX3 in this case). When the host controller does start transmitting again the interval count skips forward (e.g to a value of 902 instead of 858. In our understanding each bus interval boundary is 125us, but the Intel host controller failed to send anything for 5.512ms.ĥms is an eternity when you are expecting a transmission every 125us. The ITP packet should be send from the host each bus interval boundary to all links that aren't in a low power state. The ITP contains a timestamp value based on the Bus Interval Counter and it's value varies from 0 to 0x3FFF before it rolls over, back to zero. The Intel USB3 host controller is failing to send Isochronous Timestamp Packets (ITP) on a regular basis. National Instruments did a protocol trace for us on a similar Intel board and it looks like it is a combination of two bugs. ![]()
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